The present invention relates to an ADSL subscriber processing equipment in ATM switch, which provides various ATM services such as video conference, high speed internet connection and video-on-demand service to subscribers who uses HDSL (High-bit-rate Digital Subscriber Line).
Conventional low-speed symmetric subscriber processing equipment is not able to provide high speed service and multimedia application program service to remote users because it uses same speed for both sending and receiving. Also, since the low-speed symmetric subscriber processing equipment should be installed outside of switching equipment, ADSL subscribers cannot be controlled and the status of ADSL subscribers cannot be known from inside of the switching equipment.
An ADSL subscriber processing equipment in ATM switch is provided. The ADSL subscriber is connected with ATM layer processing device by transmit-receive cellbus and control signal bus and is connected with a number of ADSL subscribers by ADSL line.
The ADSL (asymmetric digital subscriber line) subscriber processing equipment in accordance with the present invention includes transmit-cell processing means ATM physical layer processing means ADSL processing means receive-cell processing means and central control means. The transmit-cell processing means detects ADSL subscribers on the basis of ATM parallel transmit-cell. The ATM parallel transmit-cell is supplied by the ATM layer processing device. The ATM physical layer processing means converts the parallel transmit-cell into serial data, performs signal processing on the serial data, sends the signal-processed serial data to ADSL processing means, and converts serial transmit-cell into parallel data. The serial transmit-cell is supplied by the ADSL processing means. The ADSL processing means receives serial transmit-cell from the ATM physical layer processing means, performs ADSL downstream process on the serial transmit-cell, sends the processed serial transmit-cell to ADSL subscriber through ADSL line, receives ADSL upstream from the ADSL subscriber, performs signal processing on the ADSL upstream, and sends the signal processed ADSL upstream to the ATM physical layer processing means. The receive-cell processing means receives parallel receive-cell from the ATM physical layer processing means, adds subscriber information to the parallel receive-cell, and sends information added parallel receive-cell to the ATM layer processing device. The central control means assigns addresses to the transmit-cell processing means, the ATM physical layer processing means, the ADSL processing means, and the receive-cell processing means, controls ADSL subscriber processing device by providing system clock, and generates test-cell for self loopback test.
Desirably, the ADSL subscriber processing equipment further includes transmit-receive cellbus interface means for making interface between the transmit-receive cellbus and the transmit-cell processing means/receive-cell processing means.
Desirably, the transmit-cell processing means detects ADSL subscriber to whom the transmit-cell is to be delivered on the basis of VPI (virtual pass identifier) and VCI (virtual channel identifier) in case that the transmit-cell is point-to-point transmit-cell and detects ADSL subscriber to whom the transmit-cell is to be delivered by converting VPI and VCI into real VPI and real VCI in case that the transmit-cell is point-to-multi point transmit-cell, the VPI and VCI included in the transmit-cell.
Desirably, the transmit-cell processing means includes VPI/VCI table part and Transmit-cell control part. The VPI/VCI table part stores real VPI and real VCI. The real VPI and the real VCI correspond to VPI and VCI of point-to-multi point transmit-cell respectively. The Transmit-cell control part bit-converts transmit-cell received from the transmit-receive cellbus interface means, detects ADSL subscribers to whom the transmit-cell is to be delivered on the basis of VPI and VCI of the transmit-cell, and sends the bit-converted transmit-cell to the ATM physical layer processing means.
Desirably, the transmit-cell processing means further includes transmit-cell FIFO (first-in first-out) part. The transmit-cell FIFO part stores bit-converted transmit-cell temporarily. The bit-converted transmit-cell is sent from transmit-cell control part to ATM physical layer processing means.
Desirably, the transmit-cell control part converts the 16 bit parallel transmit-cell into 8 bit parallel transmit-cell.
Desirably, the receive-cell processing means includes receive-cell control part and receive-cell FIFO (First-in First-out). The receive-cell control part analyzes receive-cell provided by the ATM physical layer processing means, adds ADSL subscriber information to the receive-cell, performs bit-conversion on the receive-cell, and sends the bit-converted receive-cell to transmit-receive cellbus interface means. The receive-cell FIFO (First-in First-out) stores receive-cell temporarily. The receive-cell is sent from the receive-cell control part to the transmit-receive cellbus interface means.
Desirably, the receive-cell processing means includes test-cell transmit-FIFO part and test-cell receive-FIFO part. The test-cell transmit-FIFO part stores test-cell and provides the test-cell to the receive-cell control part. The test-cell is generated by the central control means for use of loopback test. The test-cell receive-FIFO part receives test-cell from the receive-cell control part and sends the test-cell to the central control means.
Desirably, the transmit-receive cellbus interface means receives test-cell from the receive-cell control part, sends the test-cell to the transmit-cell control means, receives receive-cell from the receive-cell control part, sends the receive-cell to the transmit-receive cellbus, receives transmit-cell from the transmit-receive cellbus, and sends the transmit-cell to the transmit-cell control means.
Desirably, the receive-cell control means converts the 8 bit parallel receive-cell into 16 bit parallel receive-cell.
Desirably, the ADSL subscriber processing equipment further includes control signal bus interface means. The control signal bus interface means communicates various control signals, data signal, and clock signal with the ATM layer processing device through dual port RAM and sends the various control signals, data signal, and clock signal to the transmit-cell processing means, the ATM physical layer processing means, the ADSL processing means, the receive-cell processing means, and the central control means.
Desirably, the control signal bus interface means receives main clock of ECL (emitter coupled logic) level, cellbus clock of ECL level, converts the main clock of ECL level and the cellbus clock of ECL level into main clock of TTL (transistor transistor logic) level and cellbus clock of TTL level, and sends the main clock of TTL level and the cellbus clock of TTL level to the transmit-cell processing means, the ATM physical layer processing means, the ADSL processing means, the receive-cell processing means, and the central control means.
Desirably, the central control means generates function-alarm-signal and eject-alarm-signal when an error is occurred in ADSL subscriber processing device and the control signal bus interface means sends the function-alarm-signal and the eject-alarm-signal to the ATM layer processing device.
Desirably, the ADSL subscriber processing equipment transmits downstream data at speed of 1 Mbpsxcx9c8 Mbps and transmits upstream data at speed of 64 kbpsxcx9c640 Kbps. The downstream data is sent from the ATM layer processing device to ADSL subscribers and the upstream data is sent from ADSL subscribers to the ATM layer processing device.